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LTC4370 1 4370f typical a pplica t ion fea t ures descrip t ion two-supply diode-or current balancing controller the lt c ? 4370 is a two-supply current sharing controller which incorporates mosfet ideal diodes. the diodes block reverse and shoot-through currents during start-up and fault conditions. their forward voltage is adjusted to share the load currents between supplies. unlike other sharing methods, neither a share bus nor trim pins on the supply are required. the maximum mosfet voltage drop can be set with a resistor. a fast gate turn-on reduces the load voltage droop during supply switchover. if the input supply fails or is shorted, a fast turn-off minimizes reverse current transients. the controller operates with supplies from 2.9 v to 18v. for lower rail voltages, an external supply is needed at the v cc pin. enable inputs can be used to turn off the mosfet and put the controller in a low current state. status outputs indicate whether the mosfets are on or off. the load sharing function can be disabled to turn the LTC4370 into a dual ideal diode controller. 12v, 10a load share current sharing error vs supply difference a pplica t ions n shares load between two supplies n eliminates need for active control of input supplies n no share bus required n blocks reverse current n no shoot-through current during start-up or faults n 0v to 18v high side operation n enable inputs n mosfet on status outputs n dual ideal diode mode n 16-lead dfn (4mm 3mm) and msop packages n redundant power supplies n high availability systems and servers n telecom and network infrastructure l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7920013 and 8022679. additional patent pending. sum85n03-06p *optional, for fast turn-on sum85n03-06p gate1 cpo1 cpo2 gnd en1 en2 range 4370 ta01 v ina 12v v inb 12v 0.1f nc out 12v, 10a 39nf* 39nf* v in1 v cc feton1 comp feton2 out1 out2 gate2 v in2 LTC4370 2m 2m 0.18f v ina ? v inb (mv) ?750 ?20 sharing error (i vina ? i vinb )/ i l (%) ?10 0 10 ?500 ?250 2500 500 20 ?15 ?5 5 15 750 4370 ta01b
LTC4370 2 4370f a bsolu t e maxi m u m r a t ings v in1 , v in 2 , out 1, out 2 voltages ................... ?2 v to 24 v v cc voltage ............................................... ? 0.3 v to 6.5 v gate 1, gate 2 voltages ( note 3) ............... ? 0.3 v to 34 v cpo 1, cpo 2 voltages ( note 3) ................... ? 0.3 v to 34 v range voltage ................................ ?0. 3 v to v cc + 0.3 v comp voltage .............................................. ? 0.3 v to 3v en 1 , en 2 , feton 1, feton 2 voltages ......... ? 0.3 v to 24 v cpo 1, cpo 2 average current ................................. 10 ma (notes 1, 2) 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 en1 gnd v cc v in1 gate1 cpo1 out1 feton1 en2 range comp v in2 gate2 cpo2 out2 feton2 top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 125c, ja = 43c/w exposed pad (pin 17) pcb gnd connection is optional 1 2 3 4 5 6 7 8 en2 range comp v in2 gate2 cpo2 out2 feton2 16 15 14 13 12 11 10 9 en1 gnd v cc v in1 gate1 cpo1 out1 feton1 top view ms package 16-lead plastic msop t jmax = 125c, ja = 125c/w p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC4370cde#pbf LTC4370cde#trpbf 4370 16-lead (4mm 3mm) plastic dfn 0c to 70c LTC4370ide#pbf LTC4370ide#trpbf 4370 16-lead (4mm 3mm) plastic dfn C40c to 85c LTC4370cms#pbf LTC4370cms#trpbf 4370 16-lead plastic msop 0c to 70c LTC4370ims#pbf LTC4370ims#trpbf 4370 16-lead plastic msop C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ feton 1, feton 2 currents ....................................... 5 ma o perating ambient temperature range ltc 4 370 c ................................................ 0c to 70 c ltc 4 370 i ............................................. ? 40 c to 85 c storage temperature range .................. ? 65 c to 150 c lead temperature ( soldering , 10 sec ) ms p ackage ...................................................... 30 0 c
LTC4370 3 4370f e lec t rical c harac t eris t ics the l denotes those specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in1 = v in2 = 12v, out = v in , v cc open, unless otherwise noted. symbol parameter conditions min typ max units supplies v in v in1 , v in2 operating range with external v cc supply l l 2.9 0 18 v cc v v v cc(ext) v cc external supply operating range v in1 , v in2 v cc l 2.9 6 v v cc(reg) v cc regulated voltage l 4.5 5 5.5 v i in v in1 , v in2 current enabled, higher supply enabled, lower supply pull-up disabled other v in = 11.7v, both en = 0v other v in = 12.3v, both en = 0v both v in = 0v, v cc = 5v, both en = 0v both en = 1v l l l l 2.1 320 C110 80 3 450 C180 180 ma a a a i cc v cc current enabled disabled v cc = 5v, both v in = 1.2v, both en = 0v v cc = 5v, both v in = 1.2v, both en = 1v l l 2 105 2.8 220 ma a v cc(uvlo) v cc undervoltage lockout threshold v cc rising l 2.3 2.55 2.7 v v cc(hyst) v cc undervoltage lockout hysteresis l 40 120 300 mv load share v ea(os) error amplifier input offset l 0 2 mv g m(ea) error amplifier gain (Ci comp /v out ) 150 s v fr(min) minimum forward regulation voltage (v in C out) v in = 1.2v, v cc = 5v v in = 12v l l 2 2 12 25 25 50 mv mv v fr(max) maximum forward regulation voltage (v in C out) r range = 4.99k, v in = 1.2v, v cc = 5v r range = 4.99k, v in = 12v r range = 49.9k, v in = 1.2v, v cc = 5v r range = 49.9k, v in = 12v l l l l 40 45 425 440 62 75 511 524 82 100 575 590 mv mv mv mv i range range pull-up current range = 0.2v l C8.8 C10 C11.2 a v range(th) range load share disable threshold l v cc C 0.5 v cc C 0.3 v cc C 0.1 v gate drive v gate mosfet gate drive (gate C v in ) v fwd = 0.2v; i = 0, ?1a; highest v in = 12v v fwd = 0.2v; i = 0, ?1a; highest v in = 2.9v l l 10 4.5 12 7 14 9 v v t on(gate) gate1, gate2 turn-on propagation delay v fwd (= v in C out) step: C0.3v 0.3v l 0.4 1 s t off(gate) gate1, gate2 turn-off propagation delay v fwd step: 0.3v C0.3v l 0.4 1 s i gate(pk) gate1, gate2 peak pull-up current gate1, gate2 peak pull-down current v fwd = 0.4v, v gate = 0v, cpo = 17v v fwd = ?2v, v gate = 5v l l C0.9 0.9 C1.4 1.4 C1.9 1.9 a a i gate(off) gate1, gate2 off pull-down current corresponding en = 1v, v gate = 2.5v l 65 110 160 a input/output pins v en(th) en1, en2 threshold voltage en falling l 580 600 620 mv v en(th) en1, en2 threshold hysteresis l 2 8 20 mv i en en1, en2 current at 0.6v l 0 1 a i out out1, out2 current enabled disabled out n = 0v, 12v; both en = 0v both en = 1v l l C70 16 260 40 a a i cpo(up) cpo1, cpo2 pull-up current cpo = v in l C40 C70 C115 a v ol feton1, feton2 output low voltage i = 1ma i = 3ma l l 0.12 0.36 0.4 1.2 v v v oh feton1, feton2 output high voltage i = ?1a, v fwd = 1v l v cc C 1.4 v cc C 0.9 v cc C 0.5 v
LTC4370 4 4370f symbol parameter conditions min typ max units i feton feton1, feton2 leakage current at 12v l 0 1 a v gate(on) mosfet on detect threshold (gate C v in ) feton transitions high l 0.28 0.7 1.1 v typical p er f or m ance c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless otherwise specified. e lec t rical c harac t eris t ics t a = 25c, v in1 = v in2 = 12v, out = v in , v cc open, unless otherwise noted. note 3: internal clamps limit the gate and cpo pins to a minimum of 10v above, and a diode below the corresponding v in pin. driving these pins to voltages beyond the clamp may damage the device. v in current vs voltage out current vs voltage v in current vs voltage with external v cc v cc current vs voltage minimum forward regulation voltage vs v in voltage with external v cc v in (v) 0 ?0.5 0 1.5 3 6 129 15 3 0.5 2 1 2.5 18 4370 g01 i in (ma) other v in = 0v other v in = 12v v in (v) 0 ?150 i in (a) 0 150 250 1 2 43 5 300 ?100 50 ?50 100 200 6 4370 g02 v cc = 6v other v in = 0v v cc (v) 0 0 1.5 1 2 43 5 0.5 2 1 2.5 6 4370 g03 i cc (ma) both v in = 0v v out (v) 0 ?50 100 250 3 6 129 15 300 0 150 50 200 18 4370 g04 i out (a) v in (v) 0 0 15 30 1 2 43 5 20 10 25 5 4370 g05 v cc = 5v v fr(min) (mv) v cc = 3.3v
LTC4370 5 4370f typical p er f or m ance c harac t eris t ics error amplifier transfer characteristic feton output low voltage vs current feton output high voltage vs current ?v gate voltage vs current ?v gate and v cc voltages vs v in voltage maximum forward regulation voltage vs range resistor t a = 25c, v in1 = v in2 = 12v, out = v in , v cc open, unless otherwise noted. i gate (a) 0 ?3 6 ?20 ?40 ?80?60 ?100 15 0 9 3 12 ?120 4370 g06 v in = 2.9v v gate ? v in (v) v in = 18v 4 14 0 6 2 10 12 8 v in (v) 0 63 9 1512 18 4370 g07 v cc v gate ? v in , v cc (v) ?v gate r range (k) 0 0 300 600 20 40 8060 700 100 400 200 500 100 4370 g08 v fr(max) (mv) ?30 0 30 ?20 10 ?10 20 v out1 ? v out2 (mv) ?300 i comp (a) ?200 ?100 1000 200 300 4370 g09 i feton (ma) 0 0 300 600 1 2 43 700 100 400 200 500 5 4370 g10 v ol (mv) i feton (a) 0 0 3 ?2 ?4 ?8?6 5 1 4 2 ?10 4370 g11 v oh (v)
LTC4370 6 4370f comp: error amplifier compensation. connect a capacitor from this pin to gnd. the value of this capacitor should be approximately 10 to 50 times the gate capacitance (c iss ) of the mosfet switch. maintain low board leakage on this pin for best load sharing accuracy. for example , 100na of leakage current ( equal to 1 v across 10 m) increases the error amplifier offset by 0.7 mv. leave this pin open if only using ideal diode mode. cpo1, cpo2: charge pump output. connect a capacitor from this pin to the corresponding v in pin. the value of this capacitor should be approximately 10 the gate ca- pacitance (c iss ) of the mosfet switch. the charge stored on this capacitor is used to pull up the gate during a fast turn-on. leave this pin open if fast turn-on is not needed. en1, en2: enable input. keep this pin below 0.6 v to enable sharing and diode control on the corresponding supply. driving this pin high shuts off the mosfet gate (current can still flow through its body diode). the comparator has a built-in hysteresis of 8 mv. having both en pins high lowers the current consumption of the device. exposed pad ( de package only): the exposed pad may be left open or connected to device ground. feton1, feton2: mosfet status output. this pin is pulled low by an internal switch when gate is less than 0.7v above v in to indicate an off mosfet. because of this, it may also signal off if small currents are flowing through a high-g m mosfet with a large forward voltage across it. an internal 500 k resistor pulls this pin up to a diode below v cc . it may be pulled above v cc using an external pull-up. tie to gnd or leave open if unused. gate1, gate2: mosfet gate drive output.connect this pin to the gate of the external n-channel mosfet switch. an internal clamp limits the gate voltage to 12 v above, and a diode below the input supply. during fast turn-on, a 1.4 a pull-up current charges gate to cpo. during fast turn-off, a 1.4 a pull-down current discharges gate to v in . gnd: device ground. out1, out2: output voltage and current sense input. connect this pin to the input side of the supplys current sense resistor. a kelvin connection is important for ac- curate current sharing. the voltage sensed at this pin is used to control the mosfet gate. range: supply differential voltage load sharing range. connect a resistor (below 60 k) from this pin to gnd. a 10a internal pull-up current source into this resistor sets the pin voltage v range . the two supplies will typi- cally share the load current if their voltage difference is within v range . the maximum sharing range is 0.6v, obtained by leaving range open. connecting this pin to v cc disables load share control and the device behaves as a dual ideal diode controller. v cc : low voltage supply. connect a 0.1 f capacitor from this pin to ground. for v in 2.9 v this pin provides decou- pling for an internal regulator that generates a 5 v supply. for applications where both v in < 2.9 v, also connect an external supply in the 2.9v to 6v range to this pin. v in1 , v in2 : voltage sense and supply input. connect this pin to the supply side of the mosfet. the low volt- age supply v cc is generated from the higher of v in1 and v in2 . the voltage sensed at this pin is used to control the mosfet gate. p in func t ions
LTC4370 7 4370f func t ional diagra m 4370 bd charge pump1 f = 3mhz ldo charge pump2 f = 3mhz *de package only gate1 off gate2 off ? + sa1 ? + ? + ? + ? + 11 cpo1 12 gate1 13 v in1 v cc v cc v cc low v in1 g m = 150s v in2 v in1 v fr1 v fr2 v cc v supply1 10 9 out1 feton1 500k cp4 cp2 cp1 cp3 cp5 0.7v 0.6v 0.6v 2.55v 0.3v comp gate1 out1 out2 range cpo2 gate2 17 exposed pad* gnd v in2 out2 m1 v supply2 m2 ? + c1 c2 disable load share disable1 disable2 ? + ? + ? + v cc v in2 8 feton2 1 en2 14 v cc 16 en1 500k cp6 0.7v gate2 c c 10a to load r3 c vcc z r1 r2 servo adjust 3 2 6 5 15 4 7 sa2 ea + ? + ? + ? + ? + ?
LTC4370 8 4370f o pera t ion the LTC4370 controls n- channel mosfets, m 1 and m2, to share the load between two supplies. error amplifier ea compares out1 to out2 and sets the servo com- mand voltages, v fr1 and v fr2 , for servo amplifiers, sa 1 and sa2. when enabled, each servo amplifier controls the gate of the external mosfet to regulate its forward voltage drop ( v fwd = v in C out) to v fr . the combined action of ea and sa forces out1 to equal out2. having the power path resistance from out1 to the load ( r1) equal that from out2 to the load ( r 2) forces each supply to source half of the load current. the lower limit of v fr adjustment is 25 mv at higher supply voltages ( reducing to 12 mv at lower voltages to conserve power and voltage drop). the upper limit is v range + 25mv (or v range + 12 mv). v range itself is set by the 10 a pull- up current source into resistor r3. the servo adjust block ensures that only the higher supplys v fr is adjusted up while the other is pinned to the minimum. tying range to v cc ( cp5) forces both v fr to the minimum, transforming the device into a dual ideal diode controller. the servo amplifier raises the gate voltage to enhance the mosfet whenever the load current causes the drop to exceed v fr . for large output currents the mosfet gate is driven fully on and the voltage drop is equal to i fet ? r ds(on) . in the case of an input supply short-circuit, when the mosfet is conducting, a large reverse current starts flowing from the load towards the input. sa detects this failure condition as soon as it appears and turns off the mosfet by rapidly pulling down its gate. sa quickly pulls up the gate whenever it senses a large forward voltage drop. an external capacitor ( c1, c2) between the cpo and v in pins is needed for fast gate pull-up. this capacitor is charged up, at device power-up, by the internal charge-pump. the stored charge is used for the fast gate pull-up. the gate pin sources current from the cpo pin and sinks current to the v in and gnd pins. clamps limit the gate and cpo voltages to 12 v above and a diode below v in . internal switches pull the feton pins low when the gate to v in voltage is below 0.7 v to indicate that the external mosfet is off (body diode could still conduct). ldo is a low dropout regulator that generates a 5 v supply at the v cc pin from the highest v in input. when supplies below 2.9 v are being shared, an external supply in the 2.9v to 6v range is required at the v cc pin. v cc and en pin comparators, cp1 to cp3, control power passage. the mosfet is held off whenever the en pin is above 0.6 v, or the v cc pin is below 2.55 v. a high on both en pins lowers the current consumption of the device.
LTC4370 9 4370f high availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. oring diodes have been a popular means of connecting these supplies at the point of load. system uptime improves further if these paralleled supplies also share the load current. a pplica t ions i n f or m a t ion figure 1. 5v diode-or load share with status light current sharing characteristic the LTC4370 load shares the two supplies by dropping their voltage difference across the mosfets in series with them ( see figure 1). the mosfet on the lower sup- ply drops the minimum servo voltage v fr(min) (12mv or 25 mv depending on supply voltage levels), while the other mosfet drops v fr(min) plus the supply voltage difference. this equalizes both the out pin voltages, and by ohms law the current that flows through the sense resistors. figure ?2 a illustrates this. it shows the higher supplys mosfet forward voltage drop, v fwd , increasing to compensate the supply difference up to 500mv. the upper limit of the servo command adjustment is the minimum servo plus the range pin voltage (500 mv in figure 2). hence, when the two supplies differ by a volt- age equal to v range , the higher supplys v fwd is pinned at the maximum servo voltage v fr(max) . if the supplies diverge by more than v range , the out pin voltages start figure 2. load sharing characteristics 4370 f02 (2b) high r ds(on) : fully-on mosfet drops 125mv at half load ?400mv 400mv 0 525mv 25mv mosfet forward drop v in1 ? v in2 v fwd1 v fwd2 0.5i l ? r ds(on) 125mv 100mv + i l ? r s ?400mv 400mv 0 1 0 normalized current v in1 ? v in2 i 2 i 1 i 1 i 2 0.5 sharing capture range ?v in(sh) drawing is not to scale! v fr(min) i l ? r ds(on) 2r s + r ds(on) (2a) low r ds(on) : can servo 25mv minimum forward regulation voltage at half load ?500mv 500mv 0 525mv 25mv mosfet forward drop maximum m2 mosfet power dissipation v in1 ? v in2 v fwd1 v fwd2 v fr(max) v fr(min) i l ? r s ?500mv 500mv 0 1 0 normalized current v in1 ? v in2 i 2 i 1 i 1 i 2 0.5 sharing capture range ?v in(sh) v range = 500mv v range = 500mv = 2r s 1 slope = 2r s 1 slope maximum m1 mosfet power dissipation m2 sum85n03-06p d1: red led ln1251c share off d1 m1 sum85n03-06p c2 39nf gate1 cpo1 cpo2 gnd en1 en2 range 4370 f01 v ina 5v v inb 5v c vcc 0.1f r3 30.1k r4 820 c1 39nf v in1 v cc feton1 comp feton2 out1 out2 gate2v in2 LTC4370 r1 2.5m r2 2.5m out 10a c c 0.18f
LTC4370 10 4370f diverging, and so too, the supply currents. as the supply voltages separate, the entire load current is steered to the higher supply. now, the servo command across the higher supplys mosfet is folded back from the maximum to the minimum servo to minimize power dissipated in the mosfet. the sharing capture range , v in(sh) , in figure ?2 a is 500 mv, set by v range . figure 2 b will be discussed later in the mosfet selection section. range pin configuration the range pin resistor is decided by the design trade-off between the sharing capture range and the power dissipated in the mosfet. a larger r range increases the capture range at the expense of enhanced power dissipation and reduced load voltage. on the other hand, supplies with tight tolerances can afford a smaller capture range and therefore cooler operation of the mosfets. as mentioned, the upper limit of the servo command ad- justment is v range plus the minimum forward regulation voltage. since an internal 10 a pull-up current flowing through the external resistor sets v range : v fr(max) = 10a ? r range + v fr(min) (1) if r range is larger than 60k ( including the pin open state), the internal limit for the first term on the right- hand side of equation 1 is 600 mv, setting v fr(max) to 612mv or 625 mv. note that servo voltages nearing the mosfets body diode voltage may divert some or all cur- rent to the diode especially at hot temperatures. this may either cause feton to go low if v gs falls below 0.7 v, or loss of sharing control. also note that an open range pin biases itself to a voltage greater than 600mv. connecting the range pin to v cc disables the load sharing loop. the servo voltages for both mosfets are fixed at the minimum with no adjustment. the device now behaves as a dual ideal diode controller. this is handy for testing purposes. use the ltc4353 if only a dual ideal diode controller is needed. power supply configuration the LTC4370 can load share high side supplies down to 0v rail voltage. this requires powering the v cc pin with an early external supply in the 2.9 v to 6 v range. in this range of operation v in should be lower than v cc . if v cc powers up after v in , and backfeeding of v cc by the internal 5 v ldo is a concern, then a series resistor (few 100) or schottky diode limits device power dissipation and backfeeding of a low v cc supply when any v in is high. a 0.1 f bypass capacitor should also be connected between the v cc and gnd pins, close to the device. figure 3 illustrates this. if either v in operates above 2.9 v, then the external supply at v cc is not needed. the 0.1 f capacitor is still required for bypassing. start of sharing when currents are not being shared either because the load current or one of the supplies is off, the comp volt- age is railed towards 0 v or 2 v depending on the input signal to the error amplifier and its offset. for example, a pplica t ions i n f or m a t ion figure 3. power supply configurations gate1 4370 f03 0v to v cc 0v to v cc v in1 v cc gate2 v in2 LTC4370 2.9v to 6v gate1 m1 m2 m1 m2 2.9v to 18v (0v to 18v) 0v to 18v (2.9v to 18v) v in1 v cc gate2 v in2 LTC4370 c vcc 0.1f c vcc 0.1f optional or here
LTC4370 11 4370f in the absence of load current the differential input volt- age to the error amplifier is zero and the comp current is g m(ea) ? v ea(os) . before sharing can start, the comp voltage has to slew towards its operating point of 0.7v (when v in1 < v in2 ) or 1.24v (v in1 > v in2 ). this delay is determined by the differential input signal to the error amplifier ( which is v out = out1 C out2 = (i 1 ? i 2 ) ? r s ), its g m and the comp capacitor value. depending on how the currents split before converging, the delay can vary from 1 to 5 times: c c ? v comp g m(ea) ? i l ? r s figure 4 a shows the case where a 5.1 v v in1 is turned on while v in2 is at 4.9 v supplying 10 a. initially, comp is railed low to 0.1 v since v out (?i 2 ? r s ) is negative, and needs to rise to 1.24 v as the final v in1 is higher than v in2 . with v in1 off , v in is large and negative, causing the forward regulation voltage of the second supply v fr2 to be folded back to the minimum v fr(min) ( travelling from left to right in figure 2 a). as the v in magnitude decreases, v fr2 rises to the maximum v fr(max) , lowering i 2 and the load voltage. comp is around 0.7 v when v fr2 is being adjusted. when comp reaches 1.24 v, v fr2 is kept at the minimum and v fr1 is adjusted appropriately to compensate for the 0.2 v of v in . the sharing closure is smoother for the case where v in1 < v in2 since comp only has to slew to 0.7v to lower v fr2 (figure 4b). mosfet selection the LTC4370 drives n-channel mosfets to conduct the load current. the important parameters of the mosfet are its maximum drain-source voltage bv dss , maximum gate-source voltage v gs(max) , on-resistance r ds(on) , and maximum power dissipation p d(max) . if an input is connected to ground, the full supply voltage can appear across the mosfet. to survive this, the bv dss must be higher than the supply voltages. the v gs(max) rating of the mosfet should exceed 14 v since that is the upper limit of the internal gate to v in clamp. to obtain the maximum sharing capture range, the r ds( on) should be low enough for the servo amplifier to regulate the minimum forward regulation voltage across the mosfet while its conducting half of the load current. if it cannot, the gate voltage will be railed high. hence, the r ds( on) value in the mosfet data sheet should be looked up for 10 v or 4.5v gate drive depending on the v in voltage. since the out voltages are equal, the breakpoint for exact sharing in the higher r ds(on) case is: v in(sh) = v fr(max) C 0.5i l ? r ds(on) (2) a pplica t ions i n f or m a t ion figure 4. start of sharing at v in1 turn-on (4a) v in1 > v in2 (4b) v in1 < v in2 current 5a/div voltage 2v/div 4370 f04a 25ms/div v in1 = 5.1v v in2 = 4.9v i l = 10a i 2 i 1 out comp (1v/div) v in1 current 5a/div voltage 2v/div 4370 f04b 25ms/div i 2 i 1 out v in1 v in1 = 4.9v v in2 = 5.1v i l = 10a comp (0.5v/div)
LTC4370 12 4370f in figure 2b, 0.5i l ? r ds(on) is 125 mv. the higher r ds(on) rails the servo amplifier high as it cannot regulate the 25mv v fr(min) across the lower supplys mosfet. compared to figure 2 a, the sharing capture range shrinks by 100 mv (125mv C 25 mv) to 400 mv. however, the v in over which currents are shared partially stays the same at 500mv + i l ? r s . even when not maximizing sharing range, i l ? r ds(on) should be kept below 75 mv for optimum performance. the peak power dissipation in the mosfet occurs when the entire load current is being sourced by one supply with the maximum forward regulation voltage dropped across the mosfet ( as shown in figure 2 a). therefore, the p d(max) rating of the mosfet should satisfy: p d(max) i l ? v fr(max) (3) table 1 provides starting guidelines for the type of mosfet package and heat sink required at various levels of power dissipation. these are typical ranges for a room temperature ambient with no air flow. table 1. guidelines for mosfet power dissipation maximum power dissipated mosfet package heat sink 0.5w to 1w so-8 pcb 1w to 2w so-8 with exposed pad, d-pak (to-252) pcb to-220 standing in free air 2w to 4w dd-pak (to-263), to-220 pcb 4w to 10w to-220 stamping 10w to 20w to-220 casting, extrusion 20w to 50w to-247, to-3p extrusion sense resistor selection the sense resistor voltage drop dictates the current sharing accuracy. sharing error, due to the error amplifier input offset, decreases with increasing sense voltage as: i i l = |i 1 C i 2 | i l = | v ea(os) | i l ? r s = 2mv i l ? r s (4) i 1 and i 2 are the two supply currents, i l is the load current (i 1 + i 2 = i l ), r s is the sense resistor value, and v ea(os) is the input offset of the internal error amplifier. a 25mv sense resistor voltage drop with half of the load cur- rent flowing through it ( i.e., i l ? r s = 50 mv) gives a 4% sharing error. a larger sense resistance may also be needed if there is a connector in between the out pins and the load to minimize the effect of its resistance. at larger sense voltages the accuracy will be limited by the sense resistor tolerance. if sharing accuracy requirements can be relaxed, power dissipated in the sense resistor can be reduced by selecting a lower resistance. worst - case power dissipation happens at full load, i.e., when load current is not being shared. while reducing the sense resistance, note that the sharing loop does not close for load currents below v ea(os) /r s . the two sense resistors can have different values if the application does not require the load current to be shared equally between the supplies. in such a case: r s1 r s2 = i 2 i 1 (5) cpo capacitor selection the recommended value of the capacitor between the cpo and v in pins is approximately 10 the input capacitance c iss of the mosfet. a larger capacitor takes a correspondingly longer time to be charged by the internal charge pump. a smaller capacitor suffers more voltage drop during a fast gate turn-on event as it shares charge with the mosfet gate capacitance. a pplica t ions i n f or m a t ion
LTC4370 13 4370f external cpo supply the internal charge pump takes milliseconds to charge up the cpo capacitor especially during device power-up. this time can be shortened by connecting an external supply to the cpo pin. a series resistor is needed to limit the current into the internal clamp between the cpo and v in pins. the cpo supply should also be higher than the main input supply to meet the gate drive requirements of the mosfet. figure 5 shows such a 3.3 v load share application, where a 12 v supply is connected to the cpo pins through a 1 k resistor. the 1 k limits the current into the cpo pin when the v in pin is grounded. for the 8.7 v of gate drive (12v C 3.3 v), logic-level mosfets would be an appropriate choice for m1 and m2. loop stability the servo amplifier loop is compensated by the gate capacitance of the n-channel power mosfet. no further compensation components are normally required. in the case when a mosfet with less than 1 nf gate capacitance is chosen, a 1 nf compensation capacitor connected across the gate and source might be required. the load sharing control loop is compensated by the capacitor from the comp pin to ground. this capacitor should be at least 50 the input capacitance c iss of the mosfet. a larger capacitor improves stability at the ex- pense of increased sharing closure delay, while a smaller capacitor can cause the two supply currents to switch back and forth before settling. the comp capacitor can be just 10 c iss when a cpo capacitor is omitted, i.e., when fast gate turn-on is not used (see figure 6). input and output capacitance for pulsed loads for pulsed loads, the load current will be shared every cycle at frequencies below 100 hz. at higher frequencies, each cycles current may not be shared but the time average of the currents will be. bypassing capacitance on the inputs should be provided to minimize glitches and ripple. this is important since the controller tries to compensate for the supply voltage differences to achieve load sharing. sufficient load capacitance should also be provided to enhance the dc component of the load current presented to the load share circuit. it is also important to design i l ? r ds(on) below 75mv, as mentioned earlier. with very low duty cycle or very low frequency loads, the comp voltage will rail whenever the load current falls below the sharing threshold of v ea(os) / r s for hundreds of milliseconds. at the start of the next load cycle there will be a sharing closure delay as comp slews to its operating point around 0.7 v or 1.24v. to avoid this delay, maintain the load current above v ea(os) / r s . figure 5. 3.3v load share with external 12v supply powering cpo for faster start-up and refresh gate1 cpo1 cpo2 4370 f05 v ina 3.3v v inb 3.3v 12v 1k 1k to sense resistor to sense resistor m1 m2 c1 39nf c2 39nf v in1 gate2 v in2 LTC4370 a pplica t ions i n f or m a t ion figure 6. current sharing 12v supplies m2 sum85n03-06p d1: red led, ln1251c nc nc d1 m1 sum85n03-06p gate1 cpo1 cpo2 gnd en1 en2 range 4370 f06 v ina 12v v inb 12v out 10a v in1 v cc feton1 comp feton2 out1 out2 gate2 v in2 LTC4370 r1 2.5m r2 2.5m c c 0.039f c vcc 0.1f r3 47.5k r4 2.7k
LTC4370 14 4370f input transient protection when the capacitances at the input and output are very small, rapid changes in current can cause transients that exceed the 24 v absolute maximum rating of the v in and out pins. in oring applications, one surge suppressor connected from out to ground clamps all the inputs. in the absence of a surge suppressor, an output capacitance of 10 f is sufficient in most applications to prevent the transient from exceeding 24v. 12v design example this design example demonstrates the selection of components in a 12 v system with a 10 a maximum load current and 2% tolerance supplies (figure 6). that is followed by the recalculations involved for a similar 5v system (figure 1). first, calculate the r ds( on) of the mosfet to achieve the desired forward drop at full load. assuming a v fwd of 50mv: r ds(on) v fwd i load = 50mv 10a = 5m? the sum85n03-06p offers a good solution in a dd-pak (to-263) sized package with a 4.5 m r ds(on) , 30 v bv dss and 20 v v gs(max) . since 0.5i l ? r ds(on) is 22.5mv, the servo amplifier will be able to regulate the 25 mv mini- mum forward regulation voltage leading to the maximum possible sharing range set by v range . 2% of 12 v is 240 mv. the sharing capture range, v in(sh) , needs to be about 2 240mv (480 mv) to work for most supply voltage differences. a 47.5 k r3 sets v range to 475mv. equation 1 is used to calculate the maximum forward regulation voltage: v fr(max) = 10a ? 47.5k + 25mv = 500mv equation 3 gives the maximum power dissipation in the mosfet to be: p d(max) = 10a ? 500mv = 5w sufficient pcb area with air flow needs to be provided around the mosfet drain to keep its junction temperature below the 175c maximum. a 2.5 m sense resistor drops 25 mv at full load and yields an error amplifier offset induced sharing error of 2mv/(10a ? 2.5 m) or 8% (equation 4). at full load, the sense resistor dissipates 10a 2 ? 2.5 m or 250 mw. since a 12 v supply is large enough to tolerate a diode drop, fast gate turn-on is not needed. hence, the cpo capacitor is omitted. the input capacitance, c iss , of the mosfet is about 3800 pf. since fast turn-on is not used, the comp capacitor c c can be just 10 c iss at 0.039f. red led, d1, turns on when any one of the mosfets is off, indicating a break in sharing. it requires around 3 ma for good luminous intensity. accounting for a 2 v diode drop and 0.6v v ol , r4 is set to 2.7k. 5v design example for a 5v, 10 a system with 3% tolerance supplies and fast gate turn-on (figure 1), the following components need to be recalculated: r3, c1, c2, c c , and r4. r3 is set to 30.1 k to account for possible supply differences (2 ? 3% ? 5 v yields 300 mv). c1 and c2 are set to 10 c iss at 0.039 f. with fast turn-on, c c is selected closer to 50 c iss at 0.18 f. with the 5 v supply, r4 needs to be 820 to allow 3ma into the led. a pplica t ions i n f or m a t ion
LTC4370 15 4370f pcb layout considerations kelvin connection of the out pins to the sense resis- tors is important for accurate current sharing. place the mosfet as close as possible to the sense resistor. keep the traces to the mosfet wide and short to minimize resistive losses. the pcb traces associated with the power path through the mosfet should have low resistance. thermal management techniques such as sufficient drain cop- per area or heat sinks should be considered for optimal mosfet power dissipation. see figure 7. it is also important to put c vcc , the bypass capacitor, as close as possible between v cc and gnd. place c1 and c2 near the cpo and v in pins. the comp pin may need a guard ring to maintain low board leakage. figure 7. recommended pcb layout for m1, m2, c vcc , r1, r2 a pplica t ions i n f or m a t ion 4370 fo7 msop-16 r1 g s w to load current flow current flow via to ground plane d m2 dd-pak from supply b g s c vcc w d m1 dd-pak from supply a r2 track width w: 0.03 per ampere on 1oz cu foil drawing is not to scale! LTC4370
LTC4370 16 4370f typical a pplica t ions current sharing 3.3v supplies for 20a output c2 0.1f c1 0.1f gate1 cpo1 cpo2 gnd en1 en2 range 4370 ta02 v ina 3.3v 3% v inb 3.3v 3% r3 20k out 20a v in1 v cc feton1 comp feton2 out1 out2 gate2 v in2 LTC4370 r1 2m r2 2m c c 0.47f c vcc 0.1f m2 irls3034pbf m1 irls3034pbf
LTC4370 17 4370f typical a pplica t ions 12v ideal diode-or by tying range to v cc (to compare against load share). use ltc4353 if load share is not desired m2 sum85n03-06p m1 sum85n03-06p gate1 cpo1 nc nc cpo2 v cc en1 en2 gnd 4370 ta03 v ina 12v v inb 12v out 10a v in1 range feton1 comp nc feton2 out1 out2 gate2 v in2 LTC4370 c vcc 0.1f
LTC4370 18 4370f p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de16) dfn 0806 rev ? pin 1 notch r = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc
LTC4370 19 4370f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?) msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?)
LTC4370 20 4370f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0512 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1473/ ltc1473l dual powerpath tm switch driver n-channel, 4.75v to 30v/3.3v to 10v, ssop-16 package ltc1479 powerpath controller for dual battery systems three n-channel drivers, 6v to 28v, ssop-36 package ltc4352 low voltage ideal diode controller with monitoring n-channel, 0v to 18v, uv, ov, msop-12 and dfn-12 packages ltc4353 dual low voltage ideal diode controller dual n-channel, 0v to 18v, msop-16 and dfn-16 packages ltc4354 negative voltage diode-or controller and monitor dual n-channel, ?4.5v to ?80v, so-8 and dfn-8 packages ltc4355 positive high voltage ideal diode-or with supply and fuse monitors dual n-channel, 9v to 80v, so-16 and dfn-14 packages ltc4357 positive high voltage ideal diode controller n-channel, 9v to 80v, msop-8 and dfn-6 packages ltc4358 5a ideal diode internal n-channel, 9v to 26.5v, tssop-16 and dfn-14 packages ltc4411 2.6a low loss ideal diode in thinsot tm internal p-channel, 2.6v to 5.5v, 40a i q , sot-23 package ltc4412/ ltc4412hv low loss powerpath controller in thinsot p-channel, 2.5v to 28v/36v, 11a i q , sot-23 package ltc4413/ ltc4413-1 dual 2.6a, 2.5v to 5.5v, ideal diodes in dfn-10 dual internal p-channel, 2.5v to 5.5v, dfn-10 package ltc4414 36v low loss powerpath controller for large p-channel mosfet s p-channel, 3v to 36v, 30a i q , msop-8 package ltc4415 dual 4a ideal diodes with adjustable current limit dual p-channel 50m ideal diodes, 1.7v to 5.5v, 15mv forward drop, msop-16 and dfn-16 packages ltc4416/ ltc4416-1 36v low loss dual powerpath controller for large p-channel mosfets dual p-channel, 3.6v to 36v, 70a i q , msop-10 package 1.2v load share sum85n03-06p sum85n03-06p 39nf gate1 cpo1 cpo2 gnd en1 en2 range 4370 ta04 v ina 1.2v v inb 1.2v 0.1f 7.5k 5v out 39nf v in1 v cc feton1 comp feton2 out1 out2 gate2 v in2 LTC4370 2m 2m 0.18f

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